1. Field of the Invention
This invention relates to a bipolar transistor formed in a slot. More particularly, this invention relates to formation of a vertical bipolar transistor made in a slot in an integrated circuit substrate.
2. Discussion of the Prior Art
Advances in lithography have permitted line width resolution to reach micron dimensions and processing techniques have improved to the point where the reliable formation of thin films and precise etching are both possible so that smaller and more predictable feature sizes can be obtained. As a consequence, the lateral dimensions of devices are reaching micron levels and passing on into nanometer ranges resulting in a continued decrease in the ensuing density of integrated circuits.
Thus, a greater number of individual devices can be fabricated in a given area. While further increases in areal density are likely, physical, equipment, and process limits are being approached. In addition, as devices become smaller and smaller, their power ratings are reduced and the relative importance of problems such as parasitic capacitance and contamination is increased. Due to the diminishing return to be obtained from further efforts to improve areal density, it has become desirable to consider the possibility of increasing the extent of the active regions in the vertical dimension to thereby obtain performance for a device with established lateral dimensions which is equivalent to the performance of a device with greater lateral dimensions. Also higher power or higher performance devices may be obtained in this way.
As the densities of integrated circuits have increased, there has been serious consideration of using trench or slot formation processes for forming the insulating zones between individual transistors. Such an isolation technique is described in Bondur et al U.S. Pat. No. 4,104,086 as well as in Bonn U.S. patent Ser. No. 719,085 and Gwozdz U.S. patent application Ser. No. 759,621, both of which applications are assigned to the assignee of this application.
In addition to forming slots in semiconductor wafers for isolating individual devices, slots have also been considered for use as passive circuit elements. For example, it has been proposed that a slot be filled with an appropriate material so that it will function as a capacitor. See, e.g., K. Minegishi et al ., "A Sub-Micron CMOS Megabit Level Dynamic RAM Technology Using a Doped Face Trench Capacitor Cell", Proceedings, IEDM, 1983, p. 319; and T. Morie et al., "Depletion Trench Capacitor Technology for Megabit Level MOSdRAM", IEEE Electron Device Letters, v. EDL-4, No. 11, p. 411, November 1983. Such applications are possible because with appropriate filling materials a slot can be made to be conductive or insulating as required.
It has also been proposed to construct active devices in slots in a substrate. Fujitsu Japanese Patent Document No. 57-11150 discloses construction of a lateral bipolar transistor wherein an emitter region is formed by diffusing impurities into the walls of a slot formed in a substrate. A collector region is similarly formed using a slot formed in the substrate adjacent the first slot. The substrate portion between the emitter region and the collector region is said to form the base of the transistor.
In my parent application Ser. No. 576,659, assigned to the assignee of this invention and cross-reference to which is hereby made, I described and claimed the construction of a bipolar transistor in a slot in a substrate wherein a base region is first formed in the substrate walls and bottom of a first slot which is filled with a substance which will form an emitter in the slot to thereby provide a self-aligned structure with a large base-emitter surface junction. Carrier transport occurs both laterally and vertically between the emitter in the slot and the surrounding base. A second slot, providing a collector contact region, is formed in alignment with the emitter slot. A buried collector layer, located beneath the portion of the base region formed in the substrate beneath the emitter slot, communicates with the collector contact region.
Such a construction results in a high performance device having lower collector-to-base and collector-to-substrate capacitances due to the respective relationships between the physical collector and base regions and the active collector and base regions.
However, it would be desirable to construct a high performance bipolar transistor in a slot which would allow a double-sided base contact for reduced intrinsic base resistance (Rbi) and which would permit the use of an implanted collector and base in combination with a buried layer connecting the collector with a collector contact to optimize collector up down resistance, i.e., the parasitic resistance the current sees in the collector node, as well as to optimize base profile for forward transit time considerations.